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Listing of all the works of the organization. Click on the work title to get the full information.

2005
		Lozhkin S.A., Gotmanov A.N., Popov E.A., Shiganov A.E. Decomposition on the basis of universal systems of functions and its application at logic and topological VLSI synthesis
2006
		Lozhkin S.A., Romanov D.S., Gotmanov A.N., Popov E.A., Shiganov A.E. Integration of logic synthesis with a binding to library on the basis of universal systems of functions and direct methods of the generalized decomposition
		Afanasjev I.V., Venger O.V., Marchenko A.M. Using clusterization in logical synthesis
2008
		Lozhkin S.A., Romanov D.S., Gotmanov A.N., Popov E.A., Shiganov A.E. Integration of logic synthesis with binding to library in system Integro
		Ayupov A.B. Non-linear optimization framework for cell placement legalization
		Lozhkin S.A., Romanov D.S., Gotmanov A.N., Dajnyak A.B., Zapadinsky A.B., Shupletsov M.S. Probabilistic approximation of a location problem
2010
		Ryzhenko N.V. A physical synthesis to islands of cells with the same diffusion width
		Gotmanov A.N., Kishinevsky M.A., Galceran-Oms M. Synchronous elastic circuits design and its application for H.264 CABAC decoder performance optimization
2012
		Viktorov Y.O., Gotmanov A.N. Latency Analysis in Microarchitectural Models of Communication Fabrics
		Gotmanov A.N., Kishinevsky M.A., S. Chatterjee Modeling and Verification of Communication Fabrics in System on Chip Design
		Ryzhenko N.V. Standard Cell Routing via Boolean Satisfiability
2014
		Ryzhenko N.V., Sorokin A.A., Bykov S.A., Talalay M.S. Minimization of undesired layout patterns during standard cell synthesis
		Ryzhenko N.V., Sorokin A.A., Bykov S.A. Synthesis of memory units using a description of design rules via Boolean functions of layout objects
		Sorokin A.A., Ryzhenko N.V. Transistor placement at standard cell level
2016
		Talalay M.S., Ryzhenko N.V. Algorithm for design rule violation clean-up after physical design
		Bykov S.A., Ryzhenko N.V., Sorokin A.A. Automatic Determining of Auxiliary Constraints at Boundaries for Standard Cells Synthesis Flow
		Safonov I.V., Ayupov A.B., Burns S. Matrix multiplication of n-bit fixed point numbers via n/2-bit vector instructions
		Ryzhenko N.V., Bykov S.A., Sorokin A.A. Routing of Memory Bits Cells with Automated Construction of Boundary Layout Constraints
		Pechenko I.S. SoC protocols specification and validation: problems and solutions