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| Self-Timed Multiplier Performance Improvement Technique |
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| Authors |
| | Rozhdestvenskij Yu.V. |
| | Stepchenkov Yu.A. |
| | Diachenko Yu.G. |
| | Morozov N.V. |
| | Stepchenkov D.Yu. |
| | Djachenko D.Yu. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-1-82-88 |
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| Abstract |
| | Self-timed (ST) circuit's indication subcircuit largely determines its performance. This problem is especially acute in multi-bit computing ST circuits, including multiplier. The classical indication involves generating an entire ST circuit total indication output, which takes part in handshaking ST units or ST pipeline stages. Multi-bit ST circuits that implement data processing algorithms with a high parallelism degree allow the use of group indication of the ST circuit outputs resulting in bitwise signals controlling their inputs' phase. The article describes a method of accelerating the indication subcircuit operation as applied to the ST-multiplier, which implements the modified Booth algorithm and uses the two-stage Wallace tree on adders with redundant (ternary) and dual-rail ST-coding of their inputs and outputs. Group indication and bitwise input control of both Wallace tree pipeline stages provide an increase in ST-multiplier performance by 40% with a penalty of 2.3-2.5% in its hardware. |
| Keywords |
| | self-timed multiplier, redundant coding, ternary adder, Wallace tree, pipeline, indication. |
| Library reference |
| | Rozhdestvenskij Yu.V., Stepchenkov Yu.A., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu. Self-Timed Multiplier Performance Improvement Technique // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 1. P. 82-88. doi:10.31114/2078-7707-2020-1-82-88 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D028.pdf |
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