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Improvement of Ternary Self-Timed Multiplier Soft Error Tolerance
Authors
	Diachenko Yu.G.
	Stepchenkov Yu.A.
	Rozhdestvenskij Yu.V.
	Morozov N.V.
	Stepchenkov D.Yu.
	Rogdestvenskene A.V.
Date of publication
	2021
DOI
	10.31114/2078-7707-2021-2-70-76
Abstract
	Self-timed (ST) circuits are more short-term soft error tol-erant than their synchronous counterparts due to the ST coding of information signals, two-phase operation disci-pline, and request-acknowledge interaction of ST circuit's parts. Special circuitry and layout techniques make it possi-ble to increase their natural failure tolerance further. New ST signal indication principles essentially ensure this. The classical ST indication detects a single spacer state of the information ST signal. It assumes that the remaining states are only allowed working states. However, in the presence of a soft error, this assumption turns out to be incorrect. The article describes a method for increasing the noise immunity of a one-bit ternary ST adder and a multiplier based on this adder. It presents probabilistic soft error tolerance estimates for the original and improved multiplier in this respect. It is shown that due to the complication of a one-bit adder's indi-cation and the corresponding 27% increase in the hardware costs of the multiplier 5454, its failure-free operation time rises by 1.9 times.
Keywords
	soft error tolerance, self-timed multiplier, self-timed coding, ternary adder, indication.
Library reference
	Diachenko Yu.G., Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu., Rogdestvenskene A.V. Improvement of Ternary Self-Timed Multiplier Soft Error Tolerance // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 2. P. 70-76. doi:10.31114/2078-7707-2021-2-70-76
URL of paper
	http://www.mes-conference.ru/data/year2021/pdf/D015.pdf