AFE and DFE of the receiver for the CEI-25-LR and CEI-28-MR interfaces with energy-efficiency 1,45mW/Gb/s in CMOS 28nm

Larionov, A.V.; Buyakova, O.N.; Sysoeva, O.V.; Osina, S.E.

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AFE and DFE of the receiver for the CEI-25-LR and CEI-28-MR interfaces with energy-efficiency 1,45mW/Gb/s in CMOS 28nm

Authors

Date of publication

2020

DOI

10.31114/2078-7707-2020-2-118-125

Abstract

The article presents analog front end (AFE) and decision-feedback equalizer (DFE) compliant with CEI-25G-LR and CEI-28-MR interfaces. AFE includes on-die termination (ODT), low-middle continuous time linear equalizers (LMCTLE), middle continuous time linear equalizers (MCTLE) and voltage gain amplifier (VGA). Half-rate 2-taps DFE has a fully speculative architecture. AFE and DFE are capable of processing data at 25,8 Gb/s for a channel loss 27 dB without of equalizer transmitter. The circuit is designed according to the CMOS technology of 28 nm, operates from a supply voltage of 0,9 V and has an energy-efficiency 1,45 mW/Gb/s. The resulting energy-efficiency is achieved by: 1) using LMCTLE to correct intersymbol interference (ISI) in the low-frequency part of the input signal spectrum, 2) DFE is implemented without using current mode logic, 3) aggressive employ of inductors.
One of the tasks of the receiver is to restore the integrity of the input signal. The main cause of signal degradation is ISI. The hardware costs necessary to solve this problem significantly affect the energy-efficiency of the receiver. To compensate for ISI, the receiver contains CTLE and DFE [1]-[5]. In [1]-[2], the energy-efficiency of the receiver is (10÷12) mW/Gb/s. To cover the entire frequency spectrum of the received signal, broadband DFE is used, which has a large filtering order. This DFE uses high-speed power-hungry current mode logic (CML) combiners with large input and output capacitance. In [3]-[4], the energy-efficiency of the receiver (6÷8) mW/Gb/s was achieved. A fully speculative narrowband DFE is used here without any power-hungry CML circuits. Compensation of ISI in the low-frequency part of the spectrum of the input signal is carried out by using an additional low continuous time linear equalizers (LCTLE). However, LCTLE is based on the Cherry-Hooper topology, which requires two stages in the forward data path and an additional stage in the feedback loop. Also note that in [4], the DFE coefficients are regulated in a current manner, impairing energy-efficiency. In [5], a record receiver energy-efficiency of 0.66 mW/Gb/s was achieved. LCTLE is implemented in a passive manner, missing VGA, and speculative DFE has 1-tap. However, passive LCTLE reduces the bandwidth and sensitivity of the receiver, leading to a decrease in data processing speed, and too narrow DFE band limits the maximum permissible signal attenuation in the channel, which is unacceptable for the interfaces considered in this paper.
As shown in fig. 2, in this paper LMCTLE is a hybrid of two parallel branches, independently adjusting the gain in the lower and middle parts of the frequency spectrum. This solution eliminates the need for a separate circuit for the correction of low frequency ISI. Note that LMCTLE and MCTLE have a fixed DC gain, relaxing the requirements for the VGA gain adjustment range.
The 2-taps speculative half-rate DFE is implemented in a fully digital manner and is shown in Fig. 7. Comparators CP fixed four possible combinations of data followed by calculation of the actual value. Data at the DFE output is generated based on main and two post-cursors of the sequence by implementing feedback. This function is implemented on the ML latch having an input multiplexer, as shown in Fig. 8.

Keywords

transceiver, receiver, AFE, analog front end, CTLE, continuous time linear equalizer, DFE, decision-feedback equalizer, ODT, on-die termination, VGA.

Library reference

Larionov A.V., Buyakova O.N., Sysoeva O.V., Osina S.E. AFE and DFE of the receiver for the CEI-25-LR and CEI-28-MR interfaces with energy-efficiency 1,45mW/Gb/s in CMOS 28nm // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 2. P. 118-125. doi:10.31114/2078-7707-2020-2-118-125

URL of paper

http://www.mes-conference.ru/data/year2020/pdf/D018.pdf