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An improved procedure for electro-thermal simulation of the characteristics of Bi-CMOS-DMOS IC output stages  

Authors
 Petrosyants K.O.
 Kharitonov I.A.
Date of publication
 2020
DOI
 10.31114/2078-7707-2020-3-49-56

Abstract
 An improved procedure of multilevel (quasi-3D thermal analysis of IC chip - SPICE simulation of power IC circuit) electro-thermal simulation of the characteristics of the output stages of Bi-CMOS- DMOS IC is described with account for the IC layout, package and the printed circuit board parameters . The following improvements were introduced to the electro-thermal simulation flow : 1) enhanced interaction between quasi-3D thermal analysis of IC chip and electro-thermal SPICE simulation of power IC circuit - IC package temperature calculated by SPICE electro-thermal simulation were transferred to quasi-3D thermal analysis tool that allowed to reduce error in IC chip thermal simulation. 2) IC component thermal network modification – reduction (2…3 orders of value) of IC package and PCB parts thermal capacitances that allowed to substantially reduce time of SPICE electro-thermal simulation of DMOS FETs temperature variations. Example of electro-thermal simulation of the characteristics of DMOS output stages is presented. The improvements make it possible to increase the accuracy of the quasi 3D thermal simulation of IC chip and to reduce the simulation time of the combined electro-thermal simulation of the power IC output stages characteristics.
Keywords
 smart power integrated circuits; Bi-CMOS--DMOS, electro-thermal simulation, quasy 3D thermal simulation, electro-thermal SPICE models, thermal network, printed circuit board.
Library reference
 Petrosyants K.O., Kharitonov I.A. An improved procedure for electro-thermal simulation of the characteristics of Bi-CMOS-DMOS IC output stages // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 3. P. 49-56. doi:10.31114/2078-7707-2020-3-49-56
URL of paper
 http://www.mes-conference.ru/data/year2020/pdf/D117.pdf

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