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Diachenko Yu.G.

Federal Research Center “Computer Science and Control” of the RAS

Listing of all the works of the author. Click on the work title to get the full information.

2005
		Stepchenkov Yu.A., Petrukhin V.S., Diachenko Yu.G. Experience in Self-Timed Microcontroller Core Design on Basic Gate-Array
2006
		Stepchenkov Yu.A., Diachenko Yu.G., Grinfeld F.I., Morozov N.V., Plekhanov L.P., Denisov A.N., Filimonenko O.P., Fomin Yu.P. A Library of Self-Timed Elements or ASIC-Technology
2008
		Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu. Quasi Self-Timed Computing Device: Practical Implementation
		Stepchenkov Yu.A., Diachenko Yu.G., Bobkov S.G. Quasi-Delay-Insensitive Computing Device: Methodological and Algorithmic Aspects
2010
		Stepchenkov Yu.A., Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu. Self-Timed Computing Device for High-Reliable Applications
		Diachenko Yu.G., Stepchenkov D.Yu., Morozov N.V. Characterization of pseudodynamic elements
2014
		Sokolov I.A., Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G. Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Methodological Aspects
		Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Surkov A.V. Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Implementation Variants
		Bobkov S.G., Gorbunov M.S., Diachenko Yu.G., Rozhdestvenskij Yu.V., Stepchenkov Yu.A., Surkov A.V. Delay Insensitive Circuits for Low Power and Highly Reliable Microprocessors
2016
		Stepchenkov Yu.A., Diachenko Yu.G., Khilko D.V., Petrukhin V.S. Recurrent data-flow architecture: features and realization problems
		Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Stepanov B.A., Djachenko D.Yu., Rogdestvenskene A.V. Self-Timed Floating Point Multiply-Add Unit
2018
		Sokolov I.A., Rozhdestvenskij Yu.V., Diachenko Yu.G., Stepchenkov Yu.A., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu. Delay-Insensitive Floating Point Multiply-Add-Subtract Unit
2020
		Stepchenkov Yu.A., Diachenko Yu.G., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu. Hardening Self-Timed Circuit Indication against Soft Errors
		Rozhdestvenskij Yu.V., Stepchenkov Yu.A., Diachenko Yu.G., Morozov N.V., Stepchenkov D.Yu., Djachenko D.Yu. Self-Timed Multiplier Performance Improvement Technique
2021
		Diachenko Yu.G., Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Morozov N.V., Stepchenkov D.Yu., Rogdestvenskene A.V. Improvement of Ternary Self-Timed Multiplier Soft Error Tolerance
		Diachenko Yu.G., Stepchenkov Yu.A., Morozov N.V., Khilko D.V., Stepchenkov D.Yu., Shikunov Yu.I. Hardware verification of the recurrent signal processor on FPGA