Listing of all the works of the author. Click on the work title to get the full information.
| 2005 | |
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Krasnyuk A.A., Stenin V.Ya.
Simulation of SEU failures in submicronic SoS CMOS cells of memory in view of temperature effects
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| 2006 | |
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Zharkov I.A., Krasnyuk A.A., Stenin V.Ya.
Reduction of influence of single interference in submicronic trigger memory cells
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| 2008 | |
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Krasnyuk A.A., Stenin V.Ya., Cherkasov I.G., Yakovlev A.V.
The analysis of operability łą submicronic RAM CMOS VLSI at extreme thermal modes
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Stenin V.Ya., Betelin V.B., Bobkov S.G., Krasnyuk A.A., Osipenko P.N., Cherkasov I.G., Chumakov A.I., Yanenko A.V.
Prospects of using submicronic CMOS VLSI in failure-proof equipment working under impact of atmospheric neutrons
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| 2012 | |
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Katunin Yu.V., Stenin V.Ya.
The single event transient simulation of the two-phase CMOS inverters for sub-100-nm standards
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Stenin V.Ya., Stepanov P.V.
Single-Event Upset Simulation of the 65 nm 6T CMOS Static Memory Cells
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| 2014 | |
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Katunin Yu.V., Stenin V.Ya.
The two-phase 28-nm CMOS inverters in SET-tolerant logics
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Stenin V.Ya., Stepanov P.V.
The DICE cells layout design for the hardened CMOS 28 nm SRAM
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Stenin V.Ya.
Simulation of SEU transients in CMOS 28-nm DICE cells subject to single-event multi-node charge collection
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| 2016 | |
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Stenin V.Ya., Antonyuk A.V.
The logical elements of comparison for the sub-100 nm CMOS selectors of associative memory
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Stenin V.Ya., Katunin Yu.V., Stepanov P.V.
CMOS 65-nm static RAM on DICE cells with spacing groups of transistors
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| 2018 | |
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Katunin Yu.V., Stenin V.Ya.
Analysis Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory
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| 2020 | |
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Katunin Yu.V., Stenin V.Ya.
Features of single event transients in CMOS combinational logic circuits caused by charge collection from tracks of single nuclear particles
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Katunin Yu.V., Stenin V.Ya.
The CMOS majority gate when switching and the charge collection from the track of a single particle
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| 2021 | |
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Katunin Yu.V., Stenin V.Ya.
Comparative Analysis of the Error Pulses Formation at Outputs of Ttriple Majority CMOS Gates During Charge Collecting from Tracks of Single Ionizing Particles
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