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Katunin Yu.V.

National Research Nuclear University "MEPHI"

NIISI RAS

Listing of all the works of the author. Click on the work title to get the full information.

2012
		Katunin Yu.V., Stenin V.Ya. The single event transient simulation of the two-phase CMOS inverters for sub-100-nm standards
2014
		Katunin Yu.V., Levin K.E. Design of the error-correcting code blocks using the two-phase CMOS logic elements
		Katunin Yu.V., Stenin V.Ya. The two-phase 28-nm CMOS inverters in SET-tolerant logics
2016
		Stenin V.Ya., Katunin Yu.V., Stepanov P.V. CMOS 65-nm static RAM on DICE cells with spacing groups of transistors
2018
		Katunin Yu.V., Stenin V.Ya. Analysis Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory
2020
		Katunin Yu.V., Stenin V.Ya. The CMOS majority gate when switching and the charge collection from the track of a single particle
		Katunin Yu.V., Stenin V.Ya. Features of single event transients in CMOS combinational logic circuits caused by charge collection from tracks of single nuclear particles
2021
		Katunin Yu.V., Stenin V.Ya. Comparative Analysis of the Error Pulses Formation at Outputs of Ttriple Majority CMOS Gates During Charge Collecting from Tracks of Single Ionizing Particles