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Stepanov P.V.

NIISI RAS

Listing of all the works of the author. Click on the work title to get the full information.

2012
		Stenin V.Ya., Stepanov P.V. Single-Event Upset Simulation of the 65 nm 6T CMOS Static Memory Cells
2014
		Stenin V.Ya., Stepanov P.V. The DICE cells layout design for the hardened CMOS 28 nm SRAM
2016
		Stenin V.Ya., Katunin Yu.V., Stepanov P.V. CMOS 65-nm static RAM on DICE cells with spacing groups of transistors
2018
		Antonyuk A.V., Stepanov P.V. Analysis of Power Consumption of Matching Signals Summation Circuits for 65 nm CMOS Associative Memory Registers