| The Hierarchical Approach to Island Style Reconfigurable System-on-a-chip Routing |
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| Authors |
| | Zapletina M.A. |
| | Zheleznikov D.A. |
| | Gavrilov S.V. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-3-16-21 |
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| Abstract |
| | The paper considers the hierarchical two-level routing method for the island style reconfigurable systems-on-a-chip. The proposed approach can be successfully used for island style field programmable gate arrays and systems-on-a-chip also. The modified PathFinder algorithm is used for both global and detailed (switchbox) routing. The special rebalancing technique is proposed to fasten the routing algorithm and to reduce the resulting interconnects paths. Its impact was tested and analyzed. The particular attention is paid to the rules for switchbox route graphs formation as a part of a global mixed route graph model. The universal parameterized functional Tcl description for switchboxes was developed. The switchboxes of two flexibility types were considered. The computational experiments based on ISCAS-89 and LGsynth-89 benchmarks were carried out on a PC with Intel Core i7-7700 CPU and 3.60 GHz clock speed. The routing time estimation for the two-level approach showed a significant reduction of the basic mixed route graph: 5.6 times for vertices quantity. The best routing time reduction is 5.59 times and the worst is 2.52 times compared to flat routing procedure. |
| Keywords |
| | reconfigurable system-on-a-chip, RSoC, island style architecture, routing, layout synthesis, hierarchical routing, mixed route graph, switchbox routing, detailed routing. |
| Library reference |
| | Zapletina M.A., Zheleznikov D.A., Gavrilov S.V. The Hierarchical Approach to Island Style Reconfigurable System-on-a-chip Routing // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 3. P. 16-21. doi:10.31114/2078-7707-2020-3-16-21 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D040.pdf |
