| Static Timing Analysis Method with Routing Resources Estimation for Reconfigurable System-on-a-Chip |
|
 |
|
|
| Authors |
| | Gavrilov S.V. |
| | Khvatov V.M. |
| | Zheleznikov D.A. |
| | Garbulina T.V. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-2-2-8 |
|
| Abstract |
| | The well-known methods for evaluating the performance of digital circuits designed using the Field-Programmable Gate Array (FPGA) or Reconfigurable System-on-a-Chip (RSoC) use the full post-routing circuit simulation or pre-calculated interconnects delays in conjunction with the logic elements delay.
Full circuit simulation involves the use of transistors Spice-models and can be time-consuming. Modeling time is highly dependent on the circuit size and the amount of used routing resources. The delays calculation of each path also requires a lot of time, due to the large number of possible nets switching options. Therefore, a fast circuit performance estimation with a dynamic calculation of nets delays before the stage of timing verification using Spice is required.
This article shows the need for a fast circuit performance estimation at the end of various design stages: after logical synthesis in the basis of system-on-chip elements and after element placement and interconnects routing. The paper presents a step-by-step process of adding performance estimation in a whole RSoC automated design flow and describes the developed flow for a post-routing performance estimation.
This method uses software that performs static time analysis using a library of characterized logic elements in Liberty format and nets capacitive characteristics resulting from parasitic extraction. |
| Keywords |
| | Field-Programmable Gate Array, FPGA, Reconfigurable System-on-Chip, RSoC, Static Timing Analysis, Routing, Performance Estimation |
| Library reference |
| | Gavrilov S.V., Khvatov V.M., Zheleznikov D.A., Garbulina T.V. Static Timing Analysis Method with Routing Resources Estimation for Reconfigurable System-on-a-Chip // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 2. P. 2-8. doi:10.31114/2078-7707-2020-2-2-8 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D035.pdf |
