Mechanisms of Multiple Cell Upsets in Memory

Chumakov, A.I.; Sogoyan, A.V.; Boruzdina, A.B.; Smolin, A.A.; Pechenkin, A.A.

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Mechanisms of Multiple Cell Upsets in Memory

Authors

Date of publication

2016

Abstract

Multiple node events, including multiple cell upsets (MCUs), are the crucial single event effects (SEEs) under ion beam irradiation for IC technology with feature sizes less than 100 nm [1]-[4]. For dimensions of active elements of 100 nm and less, several neighboring elements can fit in the area affected by a single particle track. This MCU model is the basis of the hardening approach using interleaving of memory cells that belong to several different words and/or interleaving of nodes of several DICE storage elements [4]-[5]. Nevertheless, obtained results [6]-[7] indicate that this mechanism is not solely responsible for MCUs in SRAMs.
MCUs are traditionally categorized into physical and logical upsets [8]. The former includes upsets occurring in physically adjacent memory cells. Logical upsets include events that affect several memory cells belonging to the same word (multi-bit upsets - MBUs). This approach, in our opinion, does not sufficiently account for the principal causes of each MCU occurrence in modern memory ICs. For that reason, in this paper we present a different MCU classification based on their underlying mechanisms. The analysis allowed us to distinguish following MCU mechanisms types detected in SRAMs under heavy ion irradiation:
1. Diffusion charge collection from an ion track by separate sensitive nodes. This MCU mechanism has been studied for more than 30 years [10] and caused by charge collection from an ion track by neighboring elements [9], [11]-[12]. Analytical solutions for the diffusion component of the ionization current were found for the flat circular sensitive area approximation and three types of boundary conditions on the IC surface: Dirichlet boundary conditions, mixed boundary conditions and Robin boundary conditions.
2. Parasitic bipolar effect caused by well potential perturbation due to ion hit. MCUs of this type are geometrically tied to the well (or substrate region) in which memory cells are located. In case of an ion strike in or near the well, ionization current pulse in the well-substrate junction is formed. Due to relatively large size of this junction and high value of well resistance, the current pulse can be large enough to cause significant change of the potential in the well. As the electrostatic potential in the well drops, parasitic bipolar transistor with the base in the well region is turned on and the resulting bipolar conduction current leads to the upset of the cell [14-18]. Conducted simulations indicate that upset multiplicity in this case is determined by the distance between the strike location and a well tap, well conductivity, LET value, temperature, and several other factors.
3. Simultaneous upsets caused by incident ion and secondary ion produced by elastic scattering or nuclear reaction products. This upset mechanism is possible due to elastic or inelastic interaction of incidence particles with the nuclei of the IC materials. The nuclear reaction products can determine circuit SEU response in the low LET region when the charge generated by the primary ion is not sufficient to cause an upset [19-21]. Another important case is multiple upsets caused by an elastic recoil ion from the metallization or the substrate. The analytical expression estimating MCU probability due to Coulomb scattering in metallization and isolating layers is presented.
4. SET in control circuitry or non-stationary single event latch-up (SEL). In case of an ion hit to the decoding circuitry during the writing cycle, the selection mistake can result in the writing of the same input data at the wrong address [6]. MCU can also be initiated by the single event transient (SET) in the peripheral circuitry. Another possible reason is non-stationary SEL. Transient SEL can cause MCUs due to the rail span collapse in RAM during transient latchup current pulse. This type of MCUs cannot be effectively analyzed by computer calculation and its estimation requires an experimental research.
It is important to notice that all aforementioned effects, with the exception of functional MCUs, can take place in modern ICs simultaneously.
Accordingly, the main goal of the conducted experiments was a correct identification of MCU mechanisms in SRAMs under test. Experimental techniques were based on the combined use of ion accelerators and focused laser sources. The former were used for determination of the device’s susceptibility to MCUs, and the latter allowed the MCU sensitive regions and MCU type to be identified, if possible. The MCU mechanisms observed in several SRAMs are discussed in the paper.
The paper is a part of the research done within the government assignment #8.826.2014/K given by the ministry of education and science of Russian Federation.

Keywords

Multiple Bit Upset (MBU), Multiple Cell Upset (MCU), memory, diffusion, nuclear scattering.

Library reference

Chumakov A.I., Sogoyan A.V., Boruzdina A.B., Smolin A.A., Pechenkin A.A. Mechanisms of Multiple Cell Upsets in Memory // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 4. P. 145-152.

URL of paper

http://www.mes-conference.ru/data/year2016/pdf/D188.pdf