Home         Authors   Papers   Year of conference   Themes   Organizations        To MES conference

The method of timing optimization for FPGA at the microarchitecture level using the pipelining mechanism
Authors
	Zheleznikov D.A.
	Lyalinsky A.A.
Date of publication
	2016
Abstract
	In the article the method of timing optimization using pipelining mechanism for combinational circuits designed on FPGA, is presented. Pipelining method using retiming technique for combinational circuits is known [4]. However, this approach is limited by the presence of feedback loops - the more them in the initial circuit, the less efficiency of the technique. It should be noted that the method is used for a fixed time graph and it does not consider its changing due to variations of load and parasitic capacitances, as well as the length of the wires because of registers movement. Thus, it has a relatively low accuracy on the real circuits. This paper presents a method of combinational circuits pipelining based on iterative insertion of additional registers to reduce the length of critical paths in the time graph and achieve the desired operating frequency. In the first step the time graph using a static timing analysis is constructed. After that the critical path searching by a classical algorithm of Kirkpatrick is performed [6]. The method is focused on the practical use and can be included in the general FPGA design flow. In this article the description of method using is given, as well as a simple practical example is shown.
Keywords
	Field-Programmable Gate Array (FPGA), combinational logic, computer-aided design, pipelining.
Library reference
	Zheleznikov D.A., Lyalinsky A.A. The method of timing optimization for FPGA at the microarchitecture level using the pipelining mechanism // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 206-211.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D131.pdf