| Spread spectrum clock generator design methods |
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| Authors |
| | Sysoeva O.V. |
| | Agafonov A.E. |
| | Kirichenko P.G. |
| Date of publication |
| | 2014 |
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| Abstract |
| | This article describes design methods of spread spectrum clock generator (SSCG)
which is used in frequency synthesizer unit based on phase-locked loop (PLL).
The SSCG is designed for Serial ATA standard and provides a spread spectrum clock within -5000 ppm.
SSCG modified version has more flexible options : expanding the range of clock up / down from the center frequency
in the range of 5000 ppm and 2500 ppm.
The results of design based on 65nm CMOS technology with 1V supply voltage are confirmed by circuit simulation. |
| Keywords |
| | PLL, clock generator, spread spectrum |
| Library reference |
| | Sysoeva O.V., Agafonov A.E., Kirichenko P.G. Spread spectrum clock generator design methods // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 3. P. 77-80. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D123.pdf |
