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Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Methodological Aspects
Authors
	Sokolov I.A.
	Stepchenkov Yu.A.
	Rozhdestvenskij Yu.V.
	Diachenko Yu.G.
Date of publication
	2014
Abstract
	This report contains the approaches to designing self-timed (ST) hardware and discusses the requirements for in-system integration of the synchronous and ST units in a framework of supercomputer by an example of development of Speed-Independed Fused Multiply-Add (SIFMA) unit of gigaflops rating conforming to IEEE 754 Standard. SIFMA performs either one double precision operation, or two simultaneous single precision operations with input operands. SIFMA was designed under industrial CMOS 65-nm technology. Depending on implementation, it operates with synchronous or asynchronous environment and provides performance no less than 1 Gigaflops at latency up to 6 ns.
Keywords
	self-timed circuit, supercomputer, multiply-accumulate, adder, pipeline
Library reference
	Sokolov I.A., Stepchenkov Yu.A., Rozhdestvenskij Yu.V., Diachenko Yu.G. Speed-Independent Fused Multiply-Add Unit of Gigaflops Rating: Methodological Aspects // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 4. P. 51-56.
URL of paper
	http://www.mes-conference.ru/data/year2014/pdf/D077.pdf