| Methodology of the optimization and efficiency evaluation for the Secondary Cache |
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| Authors |
| | Aryashev S.I. |
| | Bobkov S.G. |
| | Sayapin P.V. |
| Date of publication |
| | 2014 |
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| Abstract |
| | A method for assessing the performance of the microprocessor depending on the optimization of the memory subsystem using buffer blocks was proposed. Input buffer and the store data buffer of the Secondary Cahce were described. Measurements carried on the microprocessors designed by NIISI RAS showed that buffer data blocks allowed to increase performance more than 17%. |
| Keywords |
| | Memory subsystem, cache memory, buffer block, store instruction, ECC |
| Library reference |
| | Aryashev S.I., Bobkov S.G., Sayapin P.V. Methodology of the optimization and efficiency evaluation for the Secondary Cache // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2014. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2014. Part 4. P. 13-18. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2014/pdf/D059.pdf |
