| Architecture validation tests for RTL-model of 64-bit superscalar microprocessor |
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| Authors |
| | Aryashev S.I. |
| | Nikolina N.V. |
| | Chibisov P.A. |
| Date of publication |
| | 2005 |
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| Abstract |
| | The approaches to the writing test programs are considered in the article. These approaches allow to verify compliance of RTL-model and specification. |
| Keywords |
| | microprocessor verification |
| Library reference |
| | Aryashev S.I., Nikolina N.V., Chibisov P.A. Architecture validation tests for RTL-model of 64-bit superscalar microprocessor // Problems of Perspective Microelectronic Systems Development - 2005. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2005. P. 257-262. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2005/38.doc |
