| Parameterizable matrix multiplier of fixed-point binary numbers in direct and complementary code |
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| Authors |
| | Belyaev A.A. |
| | Belyaev I.A. |
| | Petrichkovich Ya.Ya. |
| Date of publication |
| | 2021 |
| DOI |
| | 10.31114/2078-7707-2021-3-112-116 |
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| Abstract |
| | One of the most important computational operation in digital signal processing is multiplication. It is an underlying operation in telecommunication, photo and video processing, convolution neural networks, etc. The article describes the design of a matrix multiplier, the feature of which is the ability to calculate the product of two operands in a fixed-point format, each of which can be represented both in direct and in complementary code. A comparison with the traditional matrix multiplier scheme and the results of the synthesis of the proposed device using the 28 nm technology are presented. |
| Keywords |
| | multiplier, IP core, binary arithmetic, direct code, complementary code, digital signal processing. |
| Library reference |
| | Belyaev A.A., Belyaev I.A., Petrichkovich Ya.Ya. Parameterizable matrix multiplier of fixed-point binary numbers in direct and complementary code // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 3. P. 112-116. doi:10.31114/2078-7707-2021-3-112-116 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2021/pdf/D052.pdf |
