| Hardware verification of the recurrent signal processor on FPGA |
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| Authors |
| | Diachenko Yu.G. |
| | Stepchenkov Yu.A. |
| | Morozov N.V. |
| | Khilko D.V. |
| | Stepchenkov D.Yu. |
| | Shikunov Yu.I. |
| Date of publication |
| | 2021 |
| DOI |
| | 10.31114/2078-7707-2021-2-77-82 |
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| Abstract |
| | Paper represents Hybrid Architecture of Recurrent Multi-core Signal Processor (HARMSP) hardware implementation results. It describes HARMSP's register transfer level model in VHDL and hardware prototype on HAN Pilot Platform demo-board with field-programmable gate array (FPGA) Intel Arria10 SoC 10AS066K3F40E2SG. HARMSP consists of a von Neumann master processor on a control level and a dataflow processor on an operational level. Dataflow processor includes four computing cores. HARMSP's hardware model combines program or hardware implementation of the controlling processor (CP) and VHDL model of the operational level. CP's program implementation is a default option provided by Quartus software (Intel) for FPGA. FPGA Intel Arria10 SoC on demo-board provides CP's hardware implementation as Cortex-A9 two-core processor. Testing the HARMSP's hardware prototype on demo-board using an isolated word recognizer as a typical data processing application has proved that the hardware model is bit-exact with HARMSP's imitation model. The HARMSP's hardware prototype's achieved performance ensures isolated word recognizer's operation in real-time mode on demo-board. It is slightly better than the performance of the C55x (Texas Instruments) digital signal processor. |
| Keywords |
| | recurrent signal processor; hybrid multi-core architecture; VHDL model; FPGA; isolated word recognizer |
| Library reference |
| | Diachenko Yu.G., Stepchenkov Yu.A., Morozov N.V., Khilko D.V., Stepchenkov D.Yu., Shikunov Yu.I. Hardware verification of the recurrent signal processor on FPGA // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2021. Issue 2. P. 77-82. doi:10.31114/2078-7707-2021-2-77-82 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2021/pdf/D016.pdf |
