| Investigation of the characteristics of PLL components for synchronization devices in high-speed data networks |
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| Authors |
| | Makarevich A.L. |
| | Gontsov R.S. |
| | Kinash A.V. |
| | Krasavtsev N.I. |
| | Smelyanets J.V. |
| | Sokovnich S.M. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-2-147-152 |
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| Abstract |
| | the advent of optical information transmission systems with terabit and petabit transmission rates requires ever new circuitry solutions for the use of PLL systems in synchronization devices. The paper provides an analysis of the characteristics and results of circuit simulation of several options for constructing components of synchronization devices implemented within the framework of classical CMOS technology and circuitry. The implementation of the proposed solutions on CMOS transistors with design standards of 90 nm suggests that we can hope to use our results. |
| Keywords |
| | phase-lock-loop frequency control (PLL), PLL components, phase-lock detector (comparer), frequency divider, passive and active low-pass filters (LPF), SPICE models of PLL components, synchronization. |
| Library reference |
| | Makarevich A.L., Gontsov R.S., Kinash A.V., Krasavtsev N.I., Smelyanets J.V., Sokovnich S.M. Investigation of the characteristics of PLL components for synchronization devices in high-speed data networks // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 2. P. 147-152. doi:10.31114/2078-7707-2020-2-147-152 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D067.pdf |
