| Problems of Designing LDMOS-transistors Working at Increased Supply Voltage |
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| Authors |
| | Glushko A.A. |
| | Babkin S.I. |
| | Amirkhanov A.V. |
| | Zinchenko L.A. |
| | Makarchuk V.V. |
| Date of publication |
| | 2018 |
| DOI |
| | 10.31114/2078-7707-2018-3-93-97 |
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| Abstract |
| | the problems of designing LDMOS-transistors, oriented to work with a voltage of 12 V are considered. Particular attention is paid to determining the concentration of the DRIFT doping region to achieve the maximum breakdown voltage of the transistor. The main purpose of the work is to create a LDMOS structure with breakdown Voltage about 36-40 V and operating Voltage +12V. The method of the work implementation is the simulation with TCAD systems of LDMOS structure in two steps. In first step approximate simulation is carried out and the better structure satisfying the conditions of the problem. In second step, the more accurate simulation is carried out and the parameters of ion implantation steps are determined. The Breakdown Voltage dependence from impurity concentration in DRIFT area is determined. In conclusion, the experimental results are disscussed. The breakdown Voltage about 40V is achieved but DRIFT area is not used the most effectively. So as to improve the efficiency of the DRIFT area it is needed to use the initial wafers with box area no smaller than 0.5 um. |
| Keywords |
| | MOSFET, simulation, technology, VLSI |
| Library reference |
| | Glushko A.A., Babkin S.I., Amirkhanov A.V., Zinchenko L.A., Makarchuk V.V. Problems of Designing LDMOS-transistors Working at Increased Supply Voltage // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 3. P. 93-97. doi:10.31114/2078-7707-2018-3-93-97 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2018/pdf/D111.pdf |
