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MicroTESK-Based Test Program Generator for the RISC-V Architecture
Authors
	Kamkin A.S.
	Protsenko A.S.
	Smolov S.A.
	Tatarnikov A.D.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-2-2-8
Abstract
	In this paper, a specification-based test program generator for functional verification of RISC-V microprocessors is presented. The tool is based on the MicroTESK framework and consists of two main parts: (1) the formal specifications of the RISC-V ISA and (2) the ISA-independent generation core. Test programs are generated on the basis of the ISA specifications and test templates that are high-level descriptions of test scenarios. The RISC-V ISA specifications are written in nML language. They describe the syntax and semantics of the instructions. The information extracted from the specifications is used in multiple ways: to get instruction signatures to be used in test templates; to build the test coverage model that holds constraints describing execution paths of the instructions; to construct the instruction set simulator that serves as a reference model. Test templates describe how instruction sequences (test cases) are composed, and what constraints and generation methods are applied. Test templates are created using a Ruby-based domain-specific language. The generation core provides a set of components for instruction sequence composition and test data generation. They utilize random, combinatorial, and constraint-based test generation methods. The built-in instruction set simulator allows executing instructions in the process of test program generation. This allows predicting the microprocessor state to ensure the validity of the tests, to create self-checks, and to solve constraints that use state information. MicroTESK for RISC-V supports the following instruction subsets: RV32I, RV64I, RV32M, RV64M, RV32A, RV64A, RV32F, RV64F, RV32D, and RV64D. In total, the specifications cover 220 instructions. The effort required to develop the specifications constituted about 4 man-months. The specifications can be easily modified to support more instructions. MicroTESK for RISC-V includes a set of test templates that provide basic ISA coverage and demonstrate the generator facilities.
Keywords
	microprocessors; formal specifications; instruction set architecture; functional verification; test program generation; RISC-V; nML; MicroTESK.
Library reference
	Kamkin A.S., Protsenko A.S., Smolov S.A., Tatarnikov A.D. MicroTESK-Based Test Program Generator for the RISC-V Architecture // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 2. P. 2-8. doi:10.31114/2078-7707-2018-2-2-8
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D091.pdf