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Decision-feedback equalizer with active inductor for high-speed receiver
Authors
	Larionov A.V.
Date of publication
	2016
Abstract
	The paper presents decision-feedback equalizer (DFE) based on half-rate direct-feedback architecture. A feature of this work, the equalizer circuit implemented using active inductor. This increased its speed by 18 % without any additional cost for the power consumption. The 4-tap DFE is designed in CMOS 65nm technology, with power consumption 31 mW from the power source 1 V when equalizing 12.5 Gb/s data. The block designed as component of the high-speed receiver for a channel with high losses. The primary requirement of direct feedback in data recovery consists in feeding back the decision in less than one unit interval. Architecture, circuit design and technology – the way to achieve this goal. The half-rate direct-feedback architecture with latch-based equalization employed in this work. This reduces the delay in the feedback loop for the more critical of first tap, without additional hardware. This type of equalizer is a good compromise between the data rate and consumed power, successfully competing in the field high-speed communication. Active inductor used in the scheme to increase the bandwidth frequency. It is a good alternative to the classical inductance, as it takes a much smaller area and has no problem with resonance, properly functioning up to half the frequency of unity gain transistor. In addition, the benefits of an active inductor is the possibility to adjust its nominal value after manufacturing of integrated circuit. Active inductor implemented on the PMOS transistor, which provides of linear operation of the circuit in a wide range of voltage without additional power sources. The work demonstrates a significant increase in the frequency bandwidth of the critical circuit elements of DFE by replacing the resistive load to the active inductor. The time delay on the critical path equalizer decreased from 88 ps to 72 ps. To test the effectiveness of proposed solutions simulation conducted on the receiver on 10 Gb/s with DFE based on resistive load and based on active inductor. The simulation results show that the use of the active inductor allowed horizontal eye opening improved approximately on 9 ps. The resulting table shows the main characteristics of the DFE with direct-feedback architecture to this and earlier works presented.
Keywords
	equalizer, decision-feedback equalizer, receiver, transceiver, DFE, direct-feedback architecture, active inductor, CML, SSLMS, sign-sign least mean square.
Library reference
	Larionov A.V. Decision-feedback equalizer with active inductor for high-speed receiver // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 2-7.
URL of paper
	http://www.mes-conference.ru/data/year2016/pdf/D007.pdf