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| Designing PLL-blocks for systems of synchronization of integrated devices of information processing |
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| Authors |
| | Bajkov V.D. |
| | Garmash A.A. |
| | Samonov A.A. |
| | Sevryukov A.N. |
| Date of publication |
| | 2005 |
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| Abstract |
| | In the report the developed method of designing PLL with integer factor (Integer-N PLL), intended for solution of problems of synchronization of high-efficiency devices of microprocessor type with clock frequencies of 1 MHz - 1 GHz, including synchronization of standard audio of devices is presented. |
| Keywords |
| | PLL-blocks |
| Library reference |
| | Bajkov V.D., Garmash A.A., Samonov A.A., Sevryukov A.N. Designing PLL-blocks for systems of synchronization of integrated devices of information processing // Problems of Perspective Microelectronic Systems Development - 2005. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2005. P. 340-345. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2005/51.doc |
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