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A High Speed ADC with Low Power Consumption
Authors
	Agrich Yu.V.
	Lifshits V.B.
Date of publication
	2012
Abstract
	The low power high speed pipelined ADC design and evaluation results are presented. ADC can be used with wide range of the sampling rate from 10Msps up to 125Msps. ADC operates with a single supply voltage source 1.8V and consumes less than 80mW power at a maximal sampling rate. An operation mode with proportional to the sampling rate consumed current allows minimize ADC consumed current and power. The measured effective number of bit is 10.4 and measured conversion energy is 0.46pJ/bit. ADC has 1V internal reference source, but can operate with external reference voltage up to 1.6V.
Keywords
	High speed ADC, pipelined ADC, flash stage, track-and-hold unit, RSD stage.
Library reference
	Agrich Yu.V., Lifshits V.B. A High Speed ADC with Low Power Consumption // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2012. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2012. P. 362-367.
URL of paper
	http://www.mes-conference.ru/data/year2012/pdf/D122.pdf