| IP and Processor Cores Design for Navigation Application |
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| Authors |
| | Rutkevich A.V. |
| | Shishkin G.V. |
| | Steshenko V.B. |
| Date of publication |
| | 2010 |
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| Abstract |
| | This report examines trends of IP blocks designs methods taking into consideration current development trends of navigation SoC using the hardware platforms technologies. The report considers design process features taking into account market mechanisms. There are given examples of foreign and home hardware platforms for ASIC verification and navigation signal processing with its development feature. |
| Keywords |
| | SoC, IP-blocks, navigation processors. |
| Library reference |
| | Rutkevich A.V., Shishkin G.V., Steshenko V.B. IP and Processor Cores Design for Navigation Application // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 237-240. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2010/papers/m10-300-26491.pdf |
