| SystemVerilog assertions for verification and imitating modelling |
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| Authors |
| | Vetoshkin A.A. |
| Date of publication |
| | 2010 |
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| Abstract |
| | The paper describes features of assertion-based verification with using SystemVerilog (SVA). Some proposed approaches to applying SVA are also concerned in the article. Using of this method and other SV posibilities is represented by the example of solving the operand’s address calculation scheme optimization task. The article describes applying SVA to information collecting during imitating modelling of tag memory scheme. |
| Keywords |
| | SystemVerilog assertions, SVA. |
| Library reference |
| | Vetoshkin A.A. SystemVerilog assertions for verification and imitating modelling // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 48-53. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2010/papers/m10-161-46262.pdf |
