| Digital Television Decoder VLSI. The Technology of Design |
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| Authors |
| | Shevchenko P.A. |
| Date of publication |
| | 2010 |
|
| Abstract |
| | It is described the SD/HD H.264 Decoder System-on-a-Chip (SoC) design flow. The brief description, key features and possible application area are presented. The SoC architecture concept includes feature trace requirements from the end-product. These requirements incorporate characteristics of hardware including chip and reference board
and software including drivers and cross-compilation design tools. The chip structure is described. It contains third party IPs and proprietary blocks. The main problem of mixing blocks of different types into one SoC is taken onto account.
The base principles of project design and debug are considered in this article.
These principles include aspects of hardware/software chip design platform usage. This platform is a main tool for oftware/hardware IP co-verification and embedded software design for products that are based on SD/HD H.264
Decoder SoC. |
| Keywords |
| | SD/HD H.264 Decoder Television SoC, single-chip HD settop-box decoder, latest video compression technologies. |
| Library reference |
| | Shevchenko P.A. Digital Television Decoder VLSI. The Technology of Design // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2010. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2010. P. 320-325. |
| URL of paper |
| | http://www.mes-conference.ru/data/year2010/papers/m10-53-39891.pdf |
