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Evaluation of VLSI Ionization Response Under Pulsed Neutron Exposure  

Authors
 Chumakov A.I.
 Chumakov K.A.
 Diankov S.U.
Date of publication
 2022
DOI
 10.31114/2078-7707-2022-1-59-64

Abstract
 An approach for VLSI ionization response simulation under pulsed neutron irradiation due to the generation of electron-hole pairs in semiconductor structures is presented. The ionization response is determined by an integrated ionization response in power circuits (rail span collapse) of the entire chip crystal for high intensity, single event effects (SEE) occur for low intensity range and SEEs for changing effective power voltage appear in the intermediate intensity range. The criteria for determining each intensity ranges are presented.
The ionization response depends on a neutron pulse in-tensity. There are three ranges of neutron radiation intensi-ty: high, average and low intensities. The integrated ioniza-tion response in power circuits (rail span collapse) deter-mines a level of radiation hardness for high neutron pulse intensity. A sensitive volume depends on VLSI chip area and effective charge collection level. These values lie in the range between 10-4…10-1 ñm-3. Simplified approach to estimate a level of radiation hardness is considered.
Single event effects (SEE) are the main radiation effects in low neutron irradiation intensity. Traditional approach to estimate SEE rate can be applied for this region. It is necessary to take into account the typical SEE effective volumes in this case, which depend on sizes of separate VLSI elements.
The model for the intermediate region of neutron radia-tion intensities is based on SEE sensitivity parameters de-pendence on supply power voltage. The distance for these effects is twice more than high intensity one.
Keywords
 ionization effects in semiconductor, pulse neutron irradiation, rail span collapse, single event effects.
Library reference
 Chumakov A.I., Chumakov K.A., Diankov S.U. Evaluation of VLSI Ionization Response Under Pulsed Neutron Exposure // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2022. Issue 1. P. 59-64. doi:10.31114/2078-7707-2022-1-59-64
URL of paper
 http://www.mes-conference.ru/data/year2022/pdf/D005.pdf

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