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Complex Standard Cells Design Features in Advanced FinFET Technologies
Authors
	Kalashnikov V.S.
	Semenov M.Y.
Date of publication
	2022
DOI
	10.31114/2078-7707-2022-1-35-42
Abstract
	A continuous scale of planar CMOS technology results in the development of new techniques for deep submicron processes or advanced nodes. A Fin Field-Effect Transistor (FinFET) device technology becomes one of the main trends as design rules are moving to 16nm and beyond. Providing many opportunities and advantages for IC design the FinFET technology raises a lot of questions regarding reusing of current design methodology, tools, and flows. While EDA vendors do not propose any groundbreaking approach to SoC design for advanced nodes, the FinFET technology should be effectively adapted to the existing design flow with an appropriate tuning. This article provides an overview of the main challenges of using 16nm FinFET technology for standard cells design, which are an essential part of any digital flow. General recommendations for standard cells design with FinFET technology are formulated. Features of complex cells design with applying of multi-height layout architecture are presented. The proposed guidelines were proven on the example of multi-bit flip-flops design providing area effective solution for low power applications.
Keywords
	FinFET technology, advanced node, digital library, standard cell library, logic library, low power standard cell, multi-height layout architecture, multi-bit flip-flop.
Library reference
	Kalashnikov V.S., Semenov M.Y. Complex Standard Cells Design Features in Advanced FinFET Technologies // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2022. Issue 1. P. 35-42. doi:10.31114/2078-7707-2022-1-35-42
URL of paper
	http://www.mes-conference.ru/data/year2022/pdf/D001.pdf