| Logic Resynthesis Method in the FPGA Design Flow |
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| Authors |
| | Vasilyev N.O. |
| | Tiunov I.V. |
| | Ryzhova D.I. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-4-39-44 |
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| Abstract |
| | technology mapping is an important stage in the FPGA design flow. The solution obtained at this stage should be optimized for a wide range of criteria. Existing approaches often use greedy algorithms to quickly get results. However, this may lead to the result being a local minimum of the objective function.
This paper proposes a logical resynthesis method for circuits already mapped on the FPGA. The method works on a graph model, which represent the original logical circuit.
The resynthesis algorithm consists of two cycles: local and global. The local resynthesis algorithm is based on simulated annealing method (SA) and performs optimizations on the subgraphs of the original graph. At each iteration the algorithm selects one node of the subgraph and performs one of the transformations that are defined on this graph. After this algorithm decides whether to accept the decision. The probability of bad decision acceptance depends on the temperature and on the difference of the cost between the current and new states. Global resynthesis is greedy and works on the whole graph. This allows some optimizations that are not available in the local resynthesis cycle. |
| Keywords |
| | FPGA (Field-Programmable Gate Array), LUT, technology mapping, resynthesis. |
| Library reference |
| | Vasilyev N.O., Tiunov I.V., Ryzhova D.I. Logic Resynthesis Method in the FPGA Design Flow // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 4. P. 39-44. doi:10.31114/2078-7707-2020-4-39-44 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D053.pdf |
