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Hardware and software solutions to increase the reliability of combinational logic in the FPGA basis without taking into account interconnections and the I/O blocks
Authors
	Rukhlov V.S.
	Solovyev R.A.
	Kustov A.G.
Date of publication
	2020
DOI
	10.31114/2078-7707-2020-1-113-118
Abstract
	Using, developing, optimizing and improving the reliability FPGAs is an important area of direction for digital circuits. The introduction of many complex IP-blocks, improving the regular structure of programmable devices and the software component, offer flexible opportunities for developers, allowing the use of devices not only for prototyping but also as part of commercial devices. It is possible to use fault-tolerant FPGA in special-purpose equipment, in particular in the field of astronautics, avionics, control of nuclear power plants and other critical industrial facilities. Designing fault-tolerant FPGAs is an acute problem and does not have a universal solution, due to the significant redundancy laid down by manufacturers for applying traditional approaches to increasing reliability, as well as the limited number of products of this reliability class that are available on the market. This article proposes software and hardware solutions to increase the fault tolerance of combinational circuits in the basis of programmable logic integrated circuits (PLD), which can also be used for user-programmable gate arrays (FPGAs). For this, a software solution is implemented that searches for critical logic elements, an error in which will most likely affect the project outputs in the FPGA basis. The method for calculating the sensitivity coefficient of combinational logic in the FPGA basis is adapted for elements of local and global routings activated in the project, as well as other used elements. A method for evaluating the fault tolerance of combinational logics in the FPGA basis is described, and the choice of the sensitivity coefficient of the circuit to single errors as the base technology-independent metric of the fault tolerance of combinational circuits in the FPGA basis is justified. Options for minimizing the built-in redundancy of fault-tolerant FPGA elements are proposed. Experimental work was carried out on the formation of fault-tolerant designs of combinational circuits in the basis of fault-tolerant FPGAs.
Keywords
	combinational logic; field-programmable gate array (FPGA); programmable logic integrated circuits; a lookup table (LUT); logical synthesis; increased fault tolerance; computer-aided design (CAD); error injection; short-term single failures; FPGA interconnects, I / O blocks, local FPGA buses, global FPGA buses.
Library reference
	Rukhlov V.S., Solovyev R.A., Kustov A.G. Hardware and software solutions to increase the reliability of combinational logic in the FPGA basis without taking into account interconnections and the I/O blocks // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 1. P. 113-118. doi:10.31114/2078-7707-2020-1-113-118
URL of paper
	http://www.mes-conference.ru/data/year2020/pdf/D054.pdf