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Function test set formation for design correctness checking
Authors
	Ivannikov A.D.
Date of publication
	2020
DOI
	10.31114/2078-7707-2020-1-20-25
Abstract
	When designing digital systems to verify the correctness of a design, a certain set of test examples is compiled, which are fed to the computer model of the digital system design. The simulation results are checked by the developer. The paper describes the model of digital systems used in this process, on the basis of set theory, the theory of stationary dynamical systems and the theory of equivalence relations, analyzes the space of permissible input influences based on the functions performed by the digital system. Digital systems are analyzed that, during their functioning, perform a sequence of functions from a finite alphabet. An algorithm is proposed for selecting test cases for verifying the correctness (debugging) of digital systems designs when the latter perform each of the specified functions. The algorithm is based on the developer highlighting equivalence classes in the set of input actions that cause the digital system to perform a specific function from a given alphabet.
Keywords
	design automation, digital systems, design validation, functional-logical modeling, debugging tests
Library reference
	Ivannikov A.D. Function test set formation for design correctness checking // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 1. P. 20-25. doi:10.31114/2078-7707-2020-1-20-25
URL of paper
	http://www.mes-conference.ru/data/year2020/pdf/D043.pdf