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The CMOS majority gate when switching and the charge collection from the track of a single particle
Authors
	Katunin Yu.V.
	Stenin V.Ya.
Date of publication
	2020
DOI
	10.31114/2078-7707-2020-1-126-133
Abstract
	The simulation results for the triple majority gate when inputs switch during the charge collection by its transistors from the particle track are presented. The triple majority gate is based on three 2-input AND gates and one 3-input OR gate. Each of the gates (AND or OR) consists of two transistor groups. One group is a group of NMOS transistors, the other is a group of PMOS transistors. Combining transistors into groups is performed to implement the pulse quenching effect due to simultaneously charge collection by transistors of the same conductivity belonging to adjacent logic gates. Such layout optimization is performed to narrow the noise pulses caused by the impacts of particles. In this paper, we used a mixed TCAD-SPICE simulation. TCAD is preferred for simulation the physical processes of charge carrier generation and the processes of charge collection by transistors. One AND gate and one OR gate, involved in the switching process, were modeled using TCAD. Their 3D device models were designed using 65-nm CMOS bulk technology and located on the common area of the chip. The two remaining AND gates were modeled as SPICE 65-nm models. As a test effect, the charge is collected from a track directed normally to the chip surface. By default, the linear energy transfer value was 60 MeV∙cm2/mg. It is found that the duration of non-stationary state in the AND gates and OR gate, forming the majority gate, when collecting the charge and simultaneously switching the input signals, practically does not depend on the moment, when the track appears, for each specific input track point into the group of transistors. When the charge is collected before switching signals, either the gates switch ahead of time before switching signals appear at the inputs, in cases when the closed transistors begin to collect the charge, or they switch with an additional delay when the initially open transistors begin to collect the charge. When the majority gate switches ahead, the rise time of the output signal is 9-11 ps, which is less than the switching delays in operation mode without impacts of single particles, which are in the range of 35-58 ps. The switching delay of the triple majority gate increases as the moment, when the track originates, approaches to the moment, when the input signals begin to change. As result, the switching delay of the majority gate varies from 9 ps to 600 ps depending on the coordinate of the input track point and the signals at the inputs. For tracks that occur after switching the input signals of the majority gate, noise pulse is generated at the output of the gate with the duration of the non-stationary state that is typical for this input track point. The results of 3D mixed TCAD simulation confirmed a fairly good fault tolerance of the triple majority gate based on AND gates and OR gate designed using 65-nm CMOS bulk technology. These results can be used for the design of high-performance systems on the chip intended for space applications.
Keywords
	charge collection, majority gate, noise pulse, simulation, single event transient, single particle, track.
Library reference
	Katunin Yu.V., Stenin V.Ya. The CMOS majority gate when switching and the charge collection from the track of a single particle // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 1. P. 126-133. doi:10.31114/2078-7707-2020-1-126-133
URL of paper
	http://www.mes-conference.ru/data/year2020/pdf/D024.pdf