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Methods for eliminating SRAM soft and hard errors
Authors
	Shchigorev L.A.
	Shagurin I.I.
Date of publication
	2020
DOI
	10.31114/2078-7707-2020-1-148-154
Abstract
	Experts from the Semico Research Corp group estimate that in the near future up to 75% of the area of modern system-on-chips (SoC) will be occupied by elements of static random access memory (SRAM). That’s why manufacturing defects are concentrated here, it determines the yield of chips. SRAM also contains the majority of soft and hard errors during operation. This article provides a brief overview of the author’s work over the past five years in the field of combinational methods for increasing SRAM fault tolerance, and offers a method for evaluating the probability of memory correcting operation when implementing a block of components that store smaller information words. The main achievement of the work is the proposed combined method that contains single error correction and double error detection (SEC-DED), redundant columns, block dividing, and parity control. Area and read access timing penalties are investigated. When using the three methods together, the area increase is from 30 to 75%, and the read access increase is from 130 to 250% compared to the unprotected one. The increase in the total area of the memory block when divided into arrays is up to 1.5 – 2.3 times, and the decrease in the read access time amounts to from 22 to 50 %, depending on the methods used. The structures and algorithms of the built-in self-repair (BISR) memory devices for operating with various diagnostic information from the built-in self-testing (BIST) are also proposed. We also developed an algorithm for the operation of built-in self-repair memory devices that distinguishes a soft error from a hard one. An estimating method is also proposed for the upper limit probability of memory operation with division into blocks containing information words of lower bit length. It is shown that for a probability equal to 98% when using SEC-DED and two redundant columns per block, dividing into 16 blocks gives an increase in the number of fault (hard and soft) memory cells by 8 times.
Keywords
	memory built-in self-repair, memory built-in self-test, system on chip (SoC), redundancy, redundant columns, combined methods of fault tolerance, static random access memory (SRAM).
Library reference
	Shchigorev L.A., Shagurin I.I. Methods for eliminating SRAM soft and hard errors // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 1. P. 148-154. doi:10.31114/2078-7707-2020-1-148-154
URL of paper
	http://www.mes-conference.ru/data/year2020/pdf/D015.pdf