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Features of single event transients in CMOS combinational logic circuits caused by charge collection from tracks of single nuclear particles
Authors
	Katunin Yu.V.
	Stenin V.Ya.
Date of publication
	2020
DOI
	10.31114/2078-7707-2020-2-95-102
Abstract
	The results of mixed TCAD-SPICE simulation of single event transients in combinational CMOS AND and OR gates as parts of two majority gates are presented. One of majority gates is implemented on 2-input AND and OR gates, and the other is based on three 2-input AND gates and 3-input OR gate. Generating of charge carriers on the track of a particle in silicon and charge collection by transistors of logic AND and OR gates belonging to one of the logical branches of the majority gate were simulated using TCAD. Other branches of the majority gate were simulated using SPICE models. The layouts of the AND and OR gates in majority gates are optimized so that each element consists of two groups of transistors, one group is the group of NMOS transistors, the other is the group of PMOS transistors. In each group, the transistors of the AND gate (OR gate) are surrounded by transistors of inverters on both sides. Each group is a combination of several transistors with a common diffusion region, surrounded by shallow trench isolation with a depth of 400 nm. This increases the efficiency of pulse quenching during charge collection by transistors of inverter for cases of different distances from the input track points to transistors of inverter. During the simulation, the duration of noise pulses and the nature of its reduction due to the pulse quenching effect were estimated. Majority gates designed using 65-nm CMOS bulk technology were used for simulation. The simulation was performed for tracks passing along the normal to the chip surface with linear energy transfer by the particle to the track of 60 MeV∙cm2/mg. For each group, 8 track entry points are defined to get the most information about the pulse response of the circuit. When the charge from the particle track is collected by the locked transistors of the group belonging to the NAND (NOR) gate, they pass to the open state (in particular, to the inverse bias), which forms a noise pulse at the NAND (NOR) output node, which locks the transistor of the output inverter, located in the AND (OR) gate. The locked transistor of the inverter, collecting charge from the same particle track, compensates for part of the duration of the noise pulse during its propagation to the output of the AND (OR) gate. Duplicating the inverter with the location of the main and additional transistors of the inverter on both borders of the groups of NAND (NOR) transistors helps to reduce the duration of noise pulse when charge is collected from the track of an ionizing particle. Significant shortening of noise pulses occurs starting from the LET values of 30 MeV∙cm2/mg and its efficiency increases with LET increasing. Taking into account the shortening, the duration of noise pulses occurring in the majority gate is in the range of 90-350 ps. Thus, the joint charge collection by transistors located in the same diffusion area (group), surrounded by shallow trench isolation in CMOS 65-nm bulk elements, contributes to the reduction for the duration of noise pulses by 1.5-7 times. The proposed layout optimization is applicable in CMOS majority gates that remain vulnerable elements of systems implemented triple modular redundancy.
Keywords
	combinational logic, fault tolerance, ionizing particle, linear energy transfer, majority gate, noise pulse, simulation, particle track.
Library reference
	Katunin Yu.V., Stenin V.Ya. Features of single event transients in CMOS combinational logic circuits caused by charge collection from tracks of single nuclear particles // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 2. P. 95-102. doi:10.31114/2078-7707-2020-2-95-102
URL of paper
	http://www.mes-conference.ru/data/year2020/pdf/D014.pdf