| High-performance scheme of FFT calculation with conflict-free memory access |
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| Authors |
| | Poperechny P.S. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-2-81-86 |
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| Abstract |
| | The article offers the method for FFT calculation by means of unified communication scheme stage-by-stage with conflict-free memory access. There is an iterating equation for hardware and software implementation. This equation allows to construct hardware blocks or software function with 2-level loop instead of 3-level in case of traditional scheme called “in-place”. Also the reconfiguration of scheme by different samples number is provided too. The rotating multipliers are the same like in non-reconfigurable (fixed) communication scheme. So the offered approach does not required additional hardware or software resources.
The proposal approach allows to construct any purposes scheme, such as fully parallel pipelined structure for maximum performance or a sequential structure with only one butterfly node for minimum hardware. A very good instance is the structure with two butterfly nodes and four memory blocks. In this case memory access for both reading and writing is conflict free. Every two butterfly operations are taken by one clock tick. An another example is to use direct memory access controller (DMA). Thanks to conflict-free feature, DMA can access to external (refer to chip) large memory with extremely high speed for calculation large FFT transform length without chip memory using. |
| Keywords |
| | Fast Fourier Transform (FFT), Rotating Multiplier, Butterfly Node, conflict-free memory. |
| Library reference |
| | Poperechny P.S. High-performance scheme of FFT calculation with conflict-free memory access // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 2. P. 81-86. doi:10.31114/2078-7707-2020-2-81-86 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D012.pdf |
