| 10GHz Bang-Bang All Digital Phase-Locked Loop with Jitter Reduction Circuit |
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| Authors |
| | Masterov V.V. |
| Date of publication |
| | 2020 |
| DOI |
| | 10.31114/2078-7707-2020-1-106-112 |
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| Abstract |
| | 10GHz all-digital phase-locked loop implementation is presented in this article. Frequency of output signal is 10GHz with rms jitter 315fs. Built-in automatic loop gain control circuit reduces rms jitter of output signal by 43%. Algorithm of jitter reduction is based on incremental change of proportional gain achieving stochastic resonance in binary phase detector output sequence. ADPLL lock time is 12μs. Frequency acquisition and gear shifting methods are used to boost lock process. |
| Keywords |
| | ADPLL, binary phase detector, jitter, PI filter, digital oscillator, stochastic resonance. |
| Library reference |
| | Masterov V.V. 10GHz Bang-Bang All Digital Phase-Locked Loop with Jitter Reduction Circuit // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 1. P. 106-112. doi:10.31114/2078-7707-2020-1-106-112 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2020/pdf/D010.pdf |
