Home
Authors Papers Year of conference Themes Organizations To MES conference
12-bit delta-sigma ADC for monitoring high-temperature objects |
|
|
|
|
Authors |
| Korotkov A.S. |
| Morozov D.V. |
| Pilipko M.M. |
| Yenuchenko M.S. |
Date of publication |
| 2020 |
DOI |
| 10.31114/2078-7707-2020-1-95-99 |
|
Abstract |
| The development of high-temperature electronic devices [1, 2] is urgent. Delta-sigma-ADCs are used in wireless communication [3] and can be used in the sensor of high-temperature objects. The research results of an integrated circuit of a 12-bit delta-sigma ADC are presented. The operating frequency is up to 50 kHz. The clock frequency is 5 MHz. The supply voltage is 3.3 V. The operating temperature is up to 175 degrees Celsius. Dies were fabricated using Europractice X-FAB XT018 silicon-on-insulator technology. The ADC has a balanced input and consists of a delta-sigma modulator [4, 5] and a decimation filter [6]. The modulator is a cascade connection of two balanced second-order circuits based on integrators and two-bit ADCs. In feedback, two-bit DACs are used. The cascades are made on differential operational transconductance amplifiers in the form of circuits with switched capacitors with two-phase control. The second stage of the modulator reduces the quantization noise in the operating frequency band. The delta-sigma modulator operates at a clock frequency above the Nyquist frequency and converts the analog input signal into 2 two-bit pulse sequences. The modulator output signals of the ADC die were measured and processed in MATLAB. At the input frequency of 50 kHz and the differential amplitude of 500 mV the modulator provides SINAD of at least 62 dB. The decimation filter attenuates of the quantization noise outside the operating frequency band, divides the clock frequency and forms the ADC output code. The decimation filter consists of a circuit for combining the modulator outputs, a cascade integrator-comb (CIC) filter, a subtraction circuit, the 6th order IIR filter, and a decimator. The CIC filter has 5 stages and decimates by 12 times. The CIC filter bandwidth is 50 kHz, at 500 kHz the attenuation is 80 dB. The output code of the CIC filter is 17 bits larger than the input code, and the noise has a mathematical expectation equal to 0, the output signal varies from 125*64 to 125*(64+3), and the 4 most significant bits are equal to 0, so the subtraction circuit deletes them. The 6th order IIR filter has the passband of 50 kHz, at 100 kHz the attenuation is 105 dB, the passband ripple is 1 dB. The output of the IIR filter is decimated by 4 times, and the output of the ADC is the 12 most significant bits. The output signals of the ADC die were measured and processed in MATLAB. At the input frequency of 50 kHz and the differential amplitude of 500 mV the ADC provides SINAD of at least 62 dB. |
Keywords |
| delta-sigma analog-to-digital converter; decimation filter; silicon on insulator; metal oxide semiconductor. |
Library reference |
| Korotkov A.S., Morozov D.V., Pilipko M.M., Yenuchenko M.S. 12-bit delta-sigma ADC for monitoring high-temperature objects // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2020. Issue 1. P. 95-99. doi:10.31114/2078-7707-2020-1-95-99 |
URL of paper |
| http://www.mes-conference.ru/data/year2020/pdf/D008.pdf |
|
|