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About duplication of elements at VLSI layout
Authors
	Kurejchik V.M.
Date of publication
	2006
Abstract
	Problems of duplication of elements at VLSI layout are considered. Preliminary it is supposed determination of joint points and a contact of blocks in a circuit graph model. The hybrid genetic and greedy algorithm of the solution of the given problem is offered. Comparison of the developed layout design algorithms with existing ones is performed. Experiments for parallel and consecutive search of decisions were spent on the IBM PC with processor Intel Pentium IV, AMD Athlon A (0) 1500 MHz, 512 Mb of RAM, a hard disk 40 Ãá. The performed series of tests and experiments have allowed to specify theoretical estimations of time complexity of layout algorithms with duplication. Time complexity of algorithm (ÂÑÀ) is *8776; O(n) - O(n!), where n is the number of elements of the circuit.
Keywords
	VLSI layout
Library reference
	Kurejchik V.M. About duplication of elements at VLSI layout // Problems of Perspective Microelectronic Systems Development - 2006. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2006. P. 104-108.
URL of paper
	http://www.mes-conference.ru/data/year2006/17.pdf