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Authors Papers Year of conference Themes Organizations To MES conference
| Practical Aspects of Formal Verification of Networking Chips |
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| Authors |
| | Sokhatski A.A. |
| Date of publication |
| | 2018 |
| DOI |
| | 10.31114/2078-7707-2018-2-16-22 |
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| Abstract |
| | Formal Verification (FV) is becoming now important part of Design Verification (DV) especially for areas which has higher requirements for quality of chips such as networking chips which should work 24x7 without failures while re-spin cost for huge chips is high. It is difficult to cover all possible scenarios by simulation having a lot of corner cases for packet alignments, sizes, combinations of values of configuration ports and registers. Formal Verification should be able to help to improve quality and reduce Time to Market but it requires:
- Selection of right scope, candidate and method for Formal Verification;
- Addressing Formal challenges main of such is fighting with complexity and exponential grow of proof time with each proof cycle;
- Consistent Methodology to ensure verification coverage and to reduce effort.
The paper goes through those aspects basing on experience at Cisco Systems Inc. with help from OSKI Technology [1], Formal Verification service provider and Formal sign-off company [2]. The paper covers:
1) Brief review of Formal Applications while concentrating on End-to-End Formal sign-off for Design Modules along with criteria for selection of good candidates for Formal;
2) Structure of simple Formal Environment;
3) Methods helping to fight with complexity which author found especially useful for data transport modules of networking chips, such as floating pulse method, Wolper method, use of abstraction models;
4) Formal methodology aspects including:
- Document and test plan flow;
- Run Flow, Regression & Scripting;
- Coverage Flow;
- Reuse for Formal & Simulation. |
| Keywords |
| | Design Verification, Formal Verification, SystemVerilog, SVA. |
| Library reference |
| | Sokhatski A.A. Practical Aspects of Formal Verification of Networking Chips // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 2. P. 16-22. doi:10.31114/2078-7707-2018-2-16-22 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2018/pdf/D123.pdf |
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