| Verification of Memory Requests Arbitration Algorithm |
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| Authors |
| | Barskikh M.E. |
| | Esula O.I. |
| Date of publication |
| | 2018 |
| DOI |
| | 10.31114/2078-7707-2018-2-86-91 |
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| Abstract |
| | Memory controller in microprocessor provides access to external memory for a number of system components. Some requests can be set in the same time. So there is a request arbiter in the memory controller that orders requests by priorities. Arbitration algorithm [1] depends on technical requirements. It was impossible to reuse in microprocessor 1890VM9 the arbitration algorithm that was designed for the previous version 1890VM8. The main verification path in SRISA RAS is a list of programs executed by the processor. This verification path is difficult and slowly. The article considers arbitration algorithm verification that uses UVM. Masters on memory controller bus are UVM-agents, their behavior is described by using request sequence library. We used Specman e because agents’ initial code and test environment are less in compare with UVM-SV.
Microprocessor 1890VM9 has 2 levels of arbitration. The first level uses Round-Robin [2] algorithm. The second level [3] uses Least Recently Used (LRU) [4] arbitration algorithm with some modification that allows to change the bandwidth of a particular memory controller channel depending on the computational task in progress [3].
Arbitration verification was based on a test plan and managed by a test coverage. Test plan had references to technical documentation and assertion or functional coverage written in SystemVerilog. The ARM library [5] was used to check correctness. We used well-known set of assertions [6] and project specified assertions to check the correctness of the arbitration algorithm. The achievement of these points allows to see the progress of testing, and to adjust the test effects to achieve the desired result as soon as possible. The test can be adjusted by adding new test sequences or by changing constraints on parameter generation. Full execution of the test plan serves as an objective criterion for the end of the testing process.
UVM agents sent read or write requests to the memory controller. All requests were generated using a request template that had a set of required parameters. A test is successful if the read data matches the previously written data (or initial memory data) and there are no errors in the situations described by the assertions.
Emanager conducted statistics runs. In addition to error test control and regression testing, this allowed us to collect and combine coverages (code coverage and functional) for different runs. Based on the analysis of the collected information, request and test scenario limits were changed.
Described in the article verification allowed to detect 7 errors in the RTL-model of the memory controller request arbitration algorithm. In addition, 9 errors were detected in the memory controller that not related to arbitration algorithm.
The test system can be reused for verification other part of the project or in other project. |
| Keywords |
| | verification, arbitration, QoS, UVM. |
| Library reference |
| | Barskikh M.E., Esula O.I. Verification of Memory Requests Arbitration Algorithm // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 2. P. 86-91. doi:10.31114/2078-7707-2018-2-86-91 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2018/pdf/D099.pdf |
