| Methods of Achieving Test Scenario Portability Between Different Verification Environments |
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| Authors |
| | Andrianov A.V. |
| Date of publication |
| | 2018 |
| DOI |
| | 10.31114/2078-7707-2018-2-79-85 |
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| Abstract |
| | During development and verification of IP cores it is often needed to port test scenarios between different environments to check that the IP core works correctly. The article describes a set of methods of achieving portability between the following verification scenarios: RTL testbench of the IP Core, RTL model of System-on-Chip (SoC), FPGA-prototype (linux and “baremetal” alike) and the final SoC. |
| Keywords |
| | SoC, verification, verification environment, portability. |
| Library reference |
| | Andrianov A.V. Methods of Achieving Test Scenario Portability Between Different Verification Environments // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 2. P. 79-85. doi:10.31114/2078-7707-2018-2-79-85 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2018/pdf/D097.pdf |
