Non-Stable Single Event Latch-up

Chumakov, A.I.; Bobrovsky, D.V.; Pechenkin, A.A.; Savchenkov, D.V.; Sorokoumov, G.

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Non-Stable Single Event Latch-up

Authors

Date of publication

2018

DOI

10.31114/2078-7707-2018-4-177-181

Abstract

The most critical single event effect is a single event latch-up (SEL) in bulk CMOS or BiCMOS VLSI, which sometimes can cause catastrophic failures in them. Therefore, it is necessary to estimate SEL sensitivity of VLSI intended for use in electronic equipment of spacecrafts.
A common practice to estimate SEL sensitivity of VLSI is based on measurement of stationary current in power supply circuit. When its value exceeds the critical meaning we can conclude about SEL in VLSI under ion irradiation. Only stable SELs can be observed with help of this technique.
Meanwhile, we can obtain are unstable (non-stationary) SELs, namely SELs, which exist in a certain relative short period of time. Experimental results show that this time period is not exceeded several microseconds.
The main reason of nonstable SELs is the rail span collapse. Indeed, when SEL appears, current in power supply circuit increases. Thus voltage drop in substrate, wells, metal strip connections and so on raises and finally effective supply voltage can drop below holding voltage of latch-up. So we can see latch-up effect measuring transient current in power circuit and we can non observe such latch-up effect with help traditional technique. It should be noted that the value of the “internal” drop voltage depends both on the characteristics of the parasitic n-p-n-n structure and on the conditions of the experiment, in particular, the supply voltage, temperature and functional mode of VLSI.
Experimental investigation of nonstable SEL was carried out in two types of CMOS VLSI: RAM and FPGA using different facilities: proton and ion accelerators and picosecond focused laser setup.
Nonstable SELs were observed in the both VLSI. The influence of power supply voltage was carried out in RAM. The evaluation of the functional mode (static and dynamic) influence on SEL was studied in FPGA.
We obtained unusual results for FPGA. Sometimes, there were no SELs in FPGA in dynamic mode, while it had very high sensitivity in static mode. There was not SEL in FPGA in dynamic mode using a traditional technique by measure of stationary current in power supply circuit, but we could see a lot of functional upsets. FPGA had high SEL sensitivity with SEL threshold below 7 MeV.cm2/mg in the static mode. We proposed in this case that there were nonstable SELs due to high value of power supply current in dynamic mode.
We observed stable and nonstable SELs in RAM versus the value of supply voltage. For large voltage we could see stationary SEL. In the middle range of voltage there were the periodic oscillatory SELs. At last the only peak of current was occurred for relative small voltage.
The obtained experimental results show the possibility of nonstable SELs under ion irradiation. In our opinion the reason of such behavior is determined the effect of rail span collapse. Additional voltage drop can be concerned both transient latch-up current and a large value of power supply current in dynamic mode.

Keywords

ion irradiation, single event latch-up (SEL), rail span collapse, VLSI.

Library reference

Chumakov A.I., Bobrovsky D.V., Pechenkin A.A., Savchenkov D.V., Sorokoumov G. Non-Stable Single Event Latch-up // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 4. P. 177-181. doi:10.31114/2078-7707-2018-4-177-181

URL of paper

http://www.mes-conference.ru/data/year2018/pdf/D096.pdf