| | In this article we consider two types of multi-bit binary multipliers for realizing the arithmetic multiplication of two positive numbers with a fixed-point: a standard and a modified multiplier. For hardware implementation of multi-bit binary multipliers, the adders play an important role in performing the addition of partial products by multiplying two operands. So, first of all, two types of multi-bit parallel adders are analyzed for addition of two multi-bit numbers: ripple-carry adder (RCA) and parallel-prefix adder (PPA). Then, to carry out the addition of more than two operands, a carry-save adder (CSA) is implemented. Both multipliers are modeled for performing (8 × 8), (16 × 16), (32 × 32) -bit binary numbers in the Quartus II CAD environment based on the Altera EP2SGX30DF780C3 FPGAs of the Stratix-II-GX family. Their comparative analysis on hardware and time costs is performed by the following parameters: the value of the combinational ALUTs and the maximum time delay. An analysis of simulation results shows that the hardware costs of the modified multiplier are greater than those of the standard multiplier, when performing the circuit implementation of the (32 × 32)-bit multiplier, this difference is 250 ALUTs (12%). But the modified multiplier gives a gain in speed up to 55% in comparison with the standard one. In addition, the proposed structure can be scaled to a larger number of bits, for example (64 × 64), (128 × 128), (256 × 256) bits, and so on. The results show that the greater the input bits of the multipliers, the greater the percentage difference in the speed of work between them. |
