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Formation and Verification of Standard Element Libraries in the Design Flow for the Domestic FPGAs
Authors
	Khvatov V.M.
	Garbulina T.V.
	Lyalinskaya O.V.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-1-57-62
Abstract
	Domestic microelectronics industry develops within the framework of import substitution. The market of programmable logic integrated circuits (FPGAs) develops and offers various types of architectures. Using FPGA allows you to achieve high performance, significantly reduce development time, provide the ability to debug equipment and make the necessary changes during the development phase. Traditionally the software of foreign manufacturers was used for that purposes. In these conditions, an important task is to provide the possibility of designing integrated circuits (ICs) on FPGAs and automating this process through own developments in the field of software products and CAD systems. IPPM RAS has developed a route that can be integrated with foreign software products at different stages or use only components of domestic production, such as XCAD or AlphaSim, developed also in IPPM RAS. The program module XCAD is designed to automate the stages of logical synthesis, placement of elements and routing of interconnections of integrated circuits designed on the basis of FPGA. AlphaSim is intended for the analysis of electrical circuits of digital and analog-digital CMOS BIS. One of the key points is the use of standard cell libraries, which design and verification is an extensive and time-consuming task. This article describes the various types and formats of libraries used as part of the IC design flow designed for Russian FPGAs with different architectures. The design flow, all library formats and methods of their formation and verification are also presented.
Keywords
	CAD (Computer-Aided Design), Software, FPGA (field-programmable gate array), LE (logical element), LC (logical cell), library of the standard LE, liberty-file, characterization.
Library reference
	Khvatov V.M., Garbulina T.V., Lyalinskaya O.V. Formation and Verification of Standard Element Libraries in the Design Flow for the Domestic FPGAs // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 57-62. doi:10.31114/2078-7707-2018-1-57-62
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D093.pdf