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On-chip Standard Cell Delay Verification Techniques
Authors
	Kobylyatskiy A.V.
	Sergeev D.K.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-2-72-78
Abstract
	Standard cell libraries are complete products, functionality of which must be silicon-proven. However, the issue of standard cell delay validation is not enough highlighted. The concepts of on-chip delay measurement are well-known, yet there is no systematized information about existing techniques that are suitable for measuring standard cell propagation delays. In this work we present comparative analysis of such techniques that are referred to date. The techniques compared are as follows: on-chip oscilloscope, random sampling, Vernier delay line, flash, homodyne conversion, reconfigurable ring oscillator and some off-chip techniques. The benchmarks chosen are delay measurement accuracy, design complexity and area overhead. We also give a short description for each technique. From all the diversity of presented techniques the reconfigurable ring oscillator approach was chosen for implementing on our test chip. The chosen technique is area-efficient, very simple to design and provides decent accuracy (authors of the concept report 1.5 ps time resolution). The concept does not involve any analog circuits and can be designed without much effort. The test chip has been fabricated in a bulk 90-nm CMOS process. The CAD simulation of the designed structure shows maximum delay measurement error to be approximately 3 ps. We assume that the discrepancy is due to multiplexer circuit. It is supposed that timing resolution could be improved by enlarging transistor sizes and adding more symmetry to the MUX layout. The expected measurement accuracy should not be greatly less than the simulated one since possible IR drop, noise and self-heating effects were accounted.
Keywords
	VLSI, SoC, standard cell, timing, propagation delay, on-chip verification, test structure, characterization, post-silicon validation, reconfigurable ring oscillator
Library reference
	Kobylyatskiy A.V., Sergeev D.K. On-chip Standard Cell Delay Verification Techniques // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 2. P. 72-78. doi:10.31114/2078-7707-2018-2-72-78
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D077.pdf