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Algorithm of Inter-gate Resynthesis at the Transistor Level for Computer-aided Design of Microelectronic Circuits
Authors
	Ryzhova D.I.
	Vasilyev N.O.
	Zhukova T.D.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-1-193-198
Abstract
	In this article we offer inter-gate resynthesis algorithm that combine two optimization stages. At the first one method optimizes the Boolean function of given circuit. To this end, we propose graph model in which each vertex describes a logical function, and arcs describes references to arguments of functions. We use five types of logical functions: conjunction, disjunction, negation, conjunction with negation, disjunction with negation. Using this graph model provides sufficient degrees of freedom. For this graph model we use the following logical transformation: de Morgan’s transformation, decomposition of gate, merge of gates, insertion and exclusion of buffers. At the next step method optimizes layout structure of circuit. The layout optimization provides minimization of the area by removing isolating gates between the transistors. To achieve this goal, we propose to choose the orientation and position of each transistor inside the gate. If the source of the transistor is to the left of the gate and the drain is to the right, then this orientation of the transistor will be called normal. In the opposite case orientation of the transistor is considered mirror. It’s important because two transistors can be placed without isolating gate, if they have contacts connected to the same node and this contacts places next to each other. For example, two parallel connected transistors can be placed without isolating gate, if they have opposite directions (e.g. first transistor with normal orientation and second one with mirror orientation). Steps of logical and structural optimization are performed one after the other in the optimization cycle. The method was tested on a set of standard test circuits. The achieved average reduction of area is 37%. In addition, this method can be used to design fault-tolerant circuits, circuits on the FinFETs or for initial placement of FPGA elements and blocks.
Keywords
	inter-gate resynthesis, structural optimization, computer-aided design (CAD), Boolean algebra.
Library reference
	Ryzhova D.I., Vasilyev N.O., Zhukova T.D. Algorithm of Inter-gate Resynthesis at the Transistor Level for Computer-aided Design of Microelectronic Circuits // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 193-198. doi:10.31114/2078-7707-2018-1-193-198
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D073.pdf