Home
Authors Papers Year of conference Themes Organizations To MES conference
| Algorithms for Functional Correction of Boolean Circuits |
|
 |
|
|
| Authors |
| | Avtaikina M.A. |
| | Shupletsov M.S. |
| Date of publication |
| | 2018 |
| DOI |
| | 10.31114/2078-7707-2018-1-23-29 |
|
| Abstract |
| | During the IC design process, functional specifications are often modified late in the design cycle, after placement and routing are completed. However, designers are left either to manually process such modifications by hand or to restart the design process from scratch - a very costly option. Functional correction is an automated way of detecting logic difference between a modified high-level specification and an implemented design and generating patch-circuit to resolve the difference. But analyzing an entire designs is not always practical for large-scale circuits because of their size and complexity. Partitioning the design, based on two designs’ correspondence, can significantly reduce the complexity of the analysis.
In this paper, a new algorithm for functional correction is described. With partitioning large designs into corresponding smaller designs, our algorithm is able to identify multiple logic differences and modify the existing design minimally such that the new specification can be realized. The specification change is carried out within minimal time because of small sizes of analyzed designs.
Experiments show that this technique successfully implement ECO while preserving the most part of the existing logic. The size of generated patch does not exceed the sum of sizes of small designs, which hold the logic differences. Unlike the most of previous methods, the developed system can process functional correction for a design of around 100K gates in less than half an hour. |
| Keywords |
| | Boolean circuits, logic synthesis, partitioning, equivalence checking, functional correction, engineering change order, Boolean matching. |
| Library reference |
| | Avtaikina M.A., Shupletsov M.S. Algorithms for Functional Correction of Boolean Circuits // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 23-29. doi:10.31114/2078-7707-2018-1-23-29 |
| URL of paper |
| | http://www.mes-conference.ru/data/year2018/pdf/D062.pdf |
|
|
