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Testing the Performance of the Embedded Gigabit Ethernet Controller’s FPGA Prototype when working with TCP
Authors
	Slinkin D.I.
Date of publication
	2018
DOI
	10.31114/2078-7707-2018-3-138-143
Abstract
	Modern microprocessors have one or more cores. Also they can contain embedded controllers of peripheral interfaces. Field-programmable gate arrays (FPGAs) used for testing designs of microcircuits as their electric prototypes with a reduced frequency, which are usually 100-200 MHz. The 1890VM8Ja microprocessor includes an embedded Gigabit Ethernet controller. Performance evaluation of the FPGA-prototype of that controller was one of the testing tasks. The consequence of the high bandwidth of Gigabit Ethernet is the CPU loading, which could become a "bottle neck" for the entire system. At the beginning of the article, presented information to understand the factors which affects the Ethernet performance, based on the of the English-language materials. Also, some information about software and hardware CPU offloading methods is given. The task is an experimental performance evaluation of the Gigabit Ethernet Controller’s FPGA prototype to confirm the absence of internal delays in the project. In addition, efficiency of hardware CPU offloading features is of interest. The direct including of the Ethernet controller project into FPGA prototype of whole microprocessor can’t provide for good results due to limited core frequency. It is proposed to evaluate the performance of the Gigabit Ethernet controller project by installing a board with its FPGA prototype into the PCI slot of an IBM-PC compatible computer. For brevity, only the results of netperf TCP_STREAM test under Linux are given. The CPU load estimated with the "gnome-system-monitor" program, or the netperf built-in function. The results are presented, in comparison with an analog by Marvell and with an 1890VM8Ja microprocessor after its manufacturing. As a result, the receive speed of the CPU embedded Ethernet is almost equal to the FPGA prototype on IBM PC, but the transmission speed is much higher. The efficiency of the hardware CPU offloading features turned out to be moderate.
Keywords
	Gigabit Ethernet, performance, testing, microprocessor, FPGA, Linux, netperf.
Library reference
	Slinkin D.I. Testing the Performance of the Embedded Gigabit Ethernet Controller’s FPGA Prototype when working with TCP // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 3. P. 138-143. doi:10.31114/2078-7707-2018-3-138-143
URL of paper
	http://www.mes-conference.ru/data/year2018/pdf/D046.pdf